1. Field of the Invention
The present invention relates to a flash memory embedded microcomputer (simply called microcomputer from now on), and particularly to a microcomputer that carries out erasing and writing control of the flash memory using a central processing unit (called CPU below).
2. Description of Related Art
Conventionally, methods of erasing and programming a flash memory embedded in a microcomputer are roughly divided into an external programming mode that rewrites it using an external flash writer with halting its CPU, and a CPU programming mode that rewrites its contents using an embedded CPU.
FIG. 13 is a block diagram showing a configuration of a conventional flash memory embedded microcomputer with the CPU programming mode. In FIG. 13, the reference numeral 1 designates a microcomputer; 2 designates a CPU; 3 designates a flash memory section; 4 designates a RAM; 5 designate an A/D converter; 6 designates peripheral devices such as a timer, serial I/O, D/A converter, monitor timer, etc.; 7 designates an input/output port controller; and 8 designates a data bus interconnecting the CPU 2, flash memory section 3, RAM 4, A/D converter 5, peripheral devices 6, and input/output port controller 7.
The flash memory section 3 comprises a flash memory cell array 10, an address decoder 11, a sense amplifier/write circuit 12, a source circuit 13, a flash supply voltage generator 17 and a flash memory controller 18. The flash memory controller 18 includes a sequence circuit 20, a flash control register 21, a flash command register 22 and a command decoder 23, and is connected with the sense amplifier/write circuit 12 and flash supply voltage generator 17 through control lines 31 and 32.
The flash supply voltage generator 17 generates voltages to be supplied to power supply lines 35, 36 and 37 using supply voltages V.sub.pp, V.sub.cc and V.sub.ss which are externally fed through power supply ports 60, 61 and 62, and these voltages are supplied to the sense amplifier/write circuit 12, address decoder 11 and source circuit 13 through the power supply lines 35, 36 and 37.
The reference numerals 80, 81 and 8n each designate a transmission gate that selects an analog voltage from those input through input ports 70, 71 and 7n, and supplies it to an input terminal AN.sub.IN of the A/D converter 5; and 67 designates an external trigger AD.sub.TRG input port for inputting an external trigger signal that triggers the A/D converter 5 to start its conversion.
FIG. 14 is a circuit diagram showing the structure of one of the transmission gates 80, 81 and 8n in FIG. 13, in which a transmission gate 200 represented by a rhombus consists of an N-channel transistor 201 and a P-channel transistor 202.
Next, the operation in the CPU rewrite mode will be described.
a) The CPU 2 transfers a CPU rewrite control program (called boot program below) stored in the flash memory cell array 10 to the RAM 4 through the data bus 8. PA1 b) The CPU 2 jumps to the boot program in the RAM 4 to execute the following processings using the boot program. PA1 c) The CPU 2 writes "1" into the "CPU rewrite mode select bit" in the flash control register 21, thereby selecting this mode. PA1 d) The flash supply voltage generator 17 is supplied with the high voltage V.sub.pp (12.0 V) that is used for writing and erasing the flash memory from the outside of the microcomputer 1, thereby enabling the generation of the flash memory supply voltages. PA1 e) The CPU 2 writes commands to the flash command register 22. PA1 f) Decoding the commands written in the flash command register 22, the command decoder 23 instructs the sequence circuit 20 which command to be executed. PA1 g) The sequence circuit 20 carries out the sequence corresponding to the command, and causes the flash supply voltage generator 17, address decoder 11 and sense amplifier/write circuit 12 to operate at correct timings through the control lines 31 and 32. PA1 h) The flash supply voltage generator 17 generates and supplies the power supply lines 35, 36 and 37 with voltages of required levels at required timings to feed them to the sense amplifier/write circuit 12, address decoder 11 and source circuit 13.
The commands includes the following, for example.
Read command: Read the contents of the flash memory. PA0 Programming command: Write data into the flash memory. PA0 Program verification command: Read the contents of the flash memory to verify whether the data are written correctly after write operation. PA0 Erasing command: Erase the contents of the flash memory. PA0 Erasure verification command: Read the contents of the flash memory to verify whether the data are erased after erasing operation.
Fig. 15 is a table illustrating levels of the supply voltages output from the flash supply voltage generator 17 during the execution of the commands.
FIG. 16 is a block diagram showing a 1-bit memory cell and its associated portions in the flash memory cell array 10, address decoder 11, sense amplifier/write circuit 12 and source circuit 13 connected to the cell to explain the operation during the execution of the commands.
In FIG. 16, the reference numeral 127 designates a 1-bit memory cell; 130 and 131 designate an address decoder circuit and a word line buffer in the address decoder 11, respectively, which are driven by the supply voltages VDEC2 and VDEC on the power supply line 36 in FIG. 13.
The reference numerals 121, 122 and 123 designate a sense amplifier, a write circuit and a bit line selector in the sense amplifier/write circuit 12, in which the sense amplifier 121 and write circuit 122 are driven by the supply voltages VAMP and VMD, respectively. The reference numeral 133 designate a source circuit driven by the supply voltage VMS, 135 designates a word line, and 136 designates a bit line.
Next, the operation of the circuit of FIG. 16 will be described in terms of the operation modes started by the commands.
(1) Read operation mode:
As shown in FIG. 15, all the voltages are set at 5.0 V so that the word line 135 is placed at 5 V, that is, at an "H" level. Sensing the potential of the bit line 136, the sense amplifier 121 detects whether the memory cell 127 promote current (data "1") or hinders it (data "0"), and supplies the data stored in the memory cell 127 to the data bus 8.
(2) Write (programming) operation mode:
Since the supply voltage VDEC to the word line buffer 131 is set at 12 V, the word line 135 connected to the gate of the memory cell 127 is also placed at 12 V. In addition, since the supply voltage VMD is also 12 V, the bit line 136 connected to the drain is placed at about 7 V. The supply voltage VMS for the source circuit 133 is set at 0 V. In this state, data "O " is written because a large current flowing through the drain and source of the memory cell 127 induces hot electrons that are injected into its floating gate 128, which brings about the state that hinders the current.
(3) Erasing operation mode:
The supply voltage VMS for the source circuit 133 is set 12.0 V, the word line 135 is placed at 0 V or an "L" level by the address decoder circuit 130, and the bit line 136 is interrupted by a selector 123. In this state, the erasure is carried out because the electrons are drawn out of the floating gate 128 by the tunnel effect. As a result, data "1" is written that promotes the current flow.
(4) Program verification mode:
The word line 135 is placed at 6.3 V by setting VDEC at 6.3 V. On the other hand, the sense amplifier 121 operates at 5.5 V because VAMP is placed at 5.5 V. In this state, the memory cell 127 promotes current flow as compared in the read mode. In other words, the data is apt to be read as "1" or erased. Accordingly, if data "0" is not deeply written into the memory cell 127, it is not identified as "0" or written. If the data is identified as "1", the program command is executed again to iterate this operation until it is finally identified as "0" by the program verification.
(5) Erasure verification mode:
The supply voltages VDEC and VDEC2 are set at 3.5 V so that the word line 135 is placed at 3.5 V, and VAMP is placed at 4.0 V so that the sense amplifier 121 is driven at 4.0 V. In this state, the data is apt to be read as "0"(written), which is converse to the program verification mode. In other words, if the data "1" is not sufficiently erased, it is not decided as "1" (erased). The erasure verification is repeated until it is finally identified as "1" or erased.
Thus, the voltage levels of VDEC, VDEC2 and VAMP are set at intermediate potentials in the program verification mode and erasure verification mode. This enables the write level or erased depth of the memory cell 127, that is, the quantity of electrons in the floating gate or the ease of the current flow, to be controlled, that is, to be written or erased to a particular depth.
Since the write or erasure depth of the memory cell greatly depends on these voltages, the voltage level control has a critical importance in determining the characteristics of the flash memory. If the voltages shift from the design values, various problems will occur. For example, when too much writing remains undone, the draw of a small amount of electrons from the floating gate will result in the data loss which means that data "0" cannot be read, or on the contrary if the writing is too deep, the data cannot be erased easily. Similar phenomena will appear with the depth of erasure.
It is difficult, however, to adjust the flash supply voltage generator 17 because the voltage levels can be altered owing to the changes in wafer process or lines, or fluctuations in product parameters. Accordingly, it is necessary to measure the voltage levels every time a new product is developed, wafer process or line is changed, or a trouble occurs.
With such an arrangement, the conventional flash memory embedded microcomputer provides no means for measuring the voltages VAMP, VDEC, VDEC2, etc. from the outside of the chip so that they are measured directly by putting a probe on wiring on the chip. This, however, presents problems of requiring not only time and effort for fabricating a sample without a protective film or removing the protective film, but also a professional skill to put a probe on wiring of a few to one micrometer wide and a dedicated measuring instrument.
Furthermore, since the levels of these supply voltages cannot be measured in a normal wafer test, they are not measured again once they have been measured by putting the probe on the wiring, and the circuit and product parameters have been adjusted accordingly, except when significant alternation is carried out. Although the fluctuations in the voltage levels do not directly cause troubles of the product because the flash supply voltage generator 17 is designed such that it is invulnerable to various fluctuations and has a sufficient operation margin, it has a problem in that voltage level fluctuations cannot be detected which are due to variations in the product parameters, device troubles, or minute foreign substances.
In view of this, Japanese patent application laid-open Nos. 5-325580/1993 and 8-16747/1995 disclose techniques for measuring the supply voltage levels of a flash memory with an A/D converter. However, they have a complicated and expensive configuration because they have a dedicated A/D converter for measuring the voltage levels. In addition, it is not easy to read out their A/D converted results because they do not use an embedded CPU but directly write the results into registers to be read, or convert the digital data that have been once stored to analog values to be output.